1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and in particular, relates to a nonvolatile semiconductor memory device which performs erasing by injecting electrons into a floating gate electrode, and a method of manufacturing the same.
2. Description of the Background Art
As one of nonvolatile semiconductor memory devices, there has been known an EEPROM (Electrically Erasable and Programmable Read Only Memory) allowing free programming of data and allowing electrical writing and erasing of information. Although the EEPROM has an advantage that both writing and erasing can be executed electrically, it requires two transistors for each memory cell, and therefore integration to a higher degree is difficult. By this reason, there has been proposed a flash EEPROM including memory cells, each of which is formed of one transistor, and allowing electrical entire chip erasing of written electric information charges. This is disclosed, for example, in U.S. Pat. No. 4,868,619.
Further, there has been proposed a flash EEPROM of a DINOR (Divided Bit Line NOR) type as a nonvolatile semiconductor memory device which can achieve all objects of the flash EEPROM, i.e., the low cost, low voltage and low power consumption, high-speed rewriting, sector erasing and high reliability. The cell of this DINOR type is formed by employing a main/sub-bit line structure in a conventional cell of the NOR type and adding a select gate thereto.
FIG. 19 is a cross section showing a flash EEPROM of the DINOR type which has been proposed. Referring to FIG. 19, a cell of the DINOR type is provided with memory cell transistors 110 corresponding to 8 bits (8 cells) with a predetermined space therebetween. There are also formed select transistors 103 adjacent to memory cell transistors 110. A sub-bit line 102 is electrically connected to memory cell transistors 110 corresponding to 8 bits.
A main bit line 101 is connected to select transistors 103. Word lines 104 spaced by a predetermined distance are formed above main bit line 101. In the cell of the DINOR type thus constructed, low voltage and low power consumption as well as high-speed rewriting can be achieved by changing an electron injection mechanism into F-N (Fowler-Nordheim) tunneling. The low cost and sector erasing are achieved by employment of the main/sub-bit line structure and addition of a select gate. A problem of drain disturb phenomenon during sector erasing does not arise at all owing to provision of the select gate. The operation speed is high as in the conventional device.
FIG. 20 is a cross section showing a conventional cell of the DINOR type. Referring to FIG. 20, the conventional cell of the DINOR type is provided at a main surface of a P-type semiconductor substrate 1 with an N.sup.+ -drain region 2 and an N.sup.+ -source region 3 which are spaced by a predetermined distance from each other with a channel region 50 therebetween. N.sup.+ -drain region 2 is covered with N.sup.- -drain region 4. A floating gate electrode 9 is formed on channel region 50 with an insulating film 8 therebetween. A control gate electrode 11 is formed on floating gate 9 with an interlayer insulating film 10 therebetween.
FIGS. 21, 22, 24 and 26-30 are cross sections showing a process of manufacturing a memory cell portion and a peripheral circuit portion of the cell of the DINOR type shown in FIG. 20. FIG. 23 shows an impurity profile along line 100--100 in the manufacturing process shown in FIG. 22. FIG. 25 shows an impurity profile along line 200--200 in the manufacturing process shown in FIG. 24. Referring to FIGS. 21-30, description will be given on the memory cell portion and the peripheral circuit portion of the conventional cell of the DINOR type.
In the memory cell portion and peripheral circuit portion, as shown FIG. 21, a patterned SiO.sub.2 film 16 and a patterned nitride film 17 are formed at a predetermined region on the main surface of P-type semiconductor substrate 1. Using SiO.sub.2 film 16 and nitride film 17 as a mask, an element isolating oxide film 15 is formed by an LOCOS method. Thereafter, SiO.sub.2 film 16 and nitride film 17 are removed.
Referring to FIG. 22, boron (B) ion is implanted into P-type semiconductor substrate 1 with the conditions of 120-200 keV and 2.times.10.sup.12 -6.times.10.sup.12 cm.sup.-2. Thereby, a P-type channel stopper layer 18 is formed. Referring to FIG. 23, the impurity profile in the manufacturing process shown in FIG. 22 has a peak of impurity concentration of boron (B) at a predetermined depth from the surface of P-type semiconductor substrate 1.
As shown in FIG. 24, ion implantation is effected on both the memory cell portion and peripheral circuit portion, and specifically, boron is implanted into P-type semiconductor substrate 1 with the conditions of 35-50 keV and 1.times.10.sup.12 -5.times.10.sup.12 cm.sup.-2 using element isolating oxide film 15 as a mask. Thereby, a channel doped layer 19 is formed. The impurity profile in this state presents a peak caused by channel doped layer 19 and a peak caused by channel stopper layer 18.
As shown in FIG. 26, an insulating film 8 made of a tunnel oxide film of about 100 .ANG. in thickness is formed on the main surface of P-type semiconductor substrate 1 in the memory cell portion. A polycrystalline silicon layer (not shown), an ONO film (not shown) and a polycrystalline silicon layer (not shown) are successively formed on insulating film 8, and these layers are patterned to form control gate electrode 11 made of the polycrystalline silicon layer, interlayer insulating film 10 made of the ONO film and floating gate electrode 9 made of the polycrystalline silicon layer.
In the peripheral circuit portion, as shown in FIG. 27, a gate oxide film 30 is formed on the main surface of P-type semiconductor substrate 1. After forming a polycrystalline silicon layer on gate oxide film 30, the polycrystalline silicon layer is patterned to form a gate electrode 31. Gate electrode 31 in the peripheral circuit portion may be formed simultaneously with floating gate electrode 9 or control gate electrode 11 in the memory cell portion.
As shown in FIG. 28, a resist 20 is formed to cover a drain formation region in the memory cell portion. Using resist 20 and control gate electrode 11 as a mask, arsenic is ion-implanted into P-type semiconductor substrate 1 with 30-60 keV and 1.times.10.sup.15 -8.times.10.sup.15 cm.sup.-2. Thereby, source region 3 is formed. Thereafter, resist 20 is removed.
As shown in FIG. 29, a resist 21 is formed to cover source region 3 in the memory cell portion. Using resist 21 and control gate electrode 11 as a mask, arsenic is ion-implanted into P-type semiconductor substrate 1 with the conditions of 30-60 keV and 1.times.10.sup.15 -8.times.10.sup.15 cm.sup.-2, and then phosphorus (P) is ion-implanted into P-type semiconductor substrate 1 with the conditions of 30-60 keV and 1.times.10.sup.13 -1.times.10.sup.15 cm.sup.-2. Thereby, N.sup.+ -drain region 2 and N.sup.- -drain region 4 are formed. Thereafter, resist 21 is removed.
In the peripheral circuit portion, as shown in FIG. 30, N-type ion is implanted into P-type semiconductor substrate 1 using gate electrode 31 as a mask. Thereby, source/drain regions 32 and 33 of the peripheral circuit transistor are formed.
In this manner, the memory cell portion and peripheral circuit portion of the conventional DINOR type are formed.
The conventional cell of the DINOR type uses the F-N tunnel current for both writing and erasing. The cell of the DINOR type requires a device performing a single power supply operation. In order to perform writing and erasing with a single power supply of 5 V or 3.3 V, the device must be provided with a charge pump circuit for increasing the voltage. Due to provision of the charge pump circuit, the leak current which generates during writing and erasing in the memory cell must be set not to exceed the capacity of the charge pump circuit. The maximum drive capacity of the charge pump circuit depends on an area of the charge pump circuit, and is generally set to a value from about 200 to about 300 .mu.A.
FIG. 31 schematically shows a cell array structure of the conventional flash EEPROM of the DINOR type. FIG. 32 schematically shows the write operation of the flash EEPROM of the DINOR type. In the DINOR type, referring to FIGS. 31 and 32, when writing is to be effected in connection with a certain word line (WLn), information relating to the memory cell, on which writing is to be effected, among memory cells on the word line in question is sent to a latch 150. At the writing step, a charge pump circuit 151 applies a bit line bias voltage (Vd=6 V) to the bit line containing the memory cell on which the writing is effected. Thereafter, a negative bias of -8 V is applied only to word line WLn, and programming is effected on the memory cell to be programmed on the word line WLn. At this state, 0 V has been applied to the other word lines.
In the above write operation, V.sub.D =6 V is applied to the memory cells on the same bit line as the memory cell for the writing, i.e., memory cell on which the writing is performed. Thus, there exist 63 bits of nonselected cells, of which word line voltage (control gate voltage) is 0 V and bit line voltage (drain voltage) is 6 V, on the bit line on which the memory cell for the writing exists (see FIG. 32). This means that there exist up to 63.times.2K memory cells which are in the nonselected and erased state.
The leak current of such nonselected and erased memory cell will be discussed below. According to the DINOR type, the threshold voltage V.sub.TH in the erased state is set higher than the threshold voltage in the written state. Thus, in the erased state, the floating gate electrode has stored electrons. Assuming that .DELTA.V.sub.TH represents a rise of the threshold voltage in the erased state from that in the state that the floating gate has not stored electric charges, V.sub.D represents the voltage applied to the bit line in the write operation, V.sub.CC represents the voltage applied to the word line (control gate electrode), .alpha..sub.CC represents the capacitance ratio between the floating gate and control gate, and .alpha..sub.D represents the capacitance ratio between the floating gate and source region, the following formula (1) expresses a potential V.sub.FG of the floating gate in the nonselected and erased memory cell. EQU V.sub.FG =-.alpha..sub.CC .multidot..DELTA.V.sub.TH+.alpha..sub.D .multidot.V.sub.D +.alpha..sub.CC .multidot.V.sub.CC (1)
Assuming that V.sub.TH is 3 V, V.sub.D is 6 V, V.sub.CC is 0, .alpha..sub.CC is 0.6, and .alpha..sub.D is 0.1, the potential V.sub.FG of floating gate electrode goes to -1.2 V according to the above formula (1).
FIG. 33 shows a result obtained by measuring an interband tunnel current in the nonselected and erased memory cell using a memory cell which is adapted to allow direct adjustment of the potential of the floating gate electrode. The leak current was measured in the state that -1.2 V is applied to the floating gate electrode and 6 V is applied to the drain region. The interband tunnel current (leak current) was also measured with various values of the impurity concentration of N.sup.- -drain region 4 shown in FIG. 20. Referring to FIG. 33, it can be found that the interband tunnel current (leak current) is 1.times.10.sup.-8 A/cell if an N.sup.- -drain region is not formed (i.e., if impurity concentration of N.sup.- -drain region is 0). Since there exist up to 63.times.2K memory cells in the nonselected and erased state, the charge pump circuit 151 is required to have a capacity which can drive the current of 1.times.10.sup.-8 .times.63.times.2K=1.26 mA.
However, the maximum current drive capacity of the charge pump circuit 151 is about 300 .mu.A at the most as already described, and thus the above leak current exceeds the upper limit of the capacity of charge pump circuit 151. Assuming that the maximum allowable leak current of the nonselected and erased memory cell is 1/3 of the maximum capacity of the charge pump circuit, the allowable leak current per memory cell is 100 .mu.A/(63.times.2K)=793 pA. Therefore, it can be understood that the leak current per memory cell must be less than about 800 pA.
In order to reduce the interband tunnel current (leak current), N.sup.- -drain region 4 may be formed as shown in FIG. 20. As can be seen from FIG. 33, the interband tunnel current (leak current) decreases in accordance with increase of the impurity concentration of N.sup.- -drain region. In order to set the leak current to a value not more than the allowable value of 800 pA, implantation of phosphorus must be performed to attain the impurity concentration of about 3.times.10.sup.14 cm.sup.-2.
In the prior art, however, a punch-through phenomenon occurs if N.sup.- -drain region 4 is formed for preventing the interband tunnel current (leak current). The punch-through phenomenon is a phenomenon in which a depletion layer near the drain region spreads up to the source region so that the current cannot be controlled with the gate voltage. FIG. 34 shows punch-through characteristics in a memory cell of the conventional flash EEPROM. Referring to FIG. 34, if the gate length is about 0.6 .mu.m, it is necessary to ensure the breakdown characteristics with the gate length of about 0.55 .mu.m when actually forming the device, taking processing tolerance and others into consideration. More specifically, as shown in FIG. 34, the breakdown voltage not less than 6 V (i.e., not less than bias voltage in the write operation) must be ensured with the gate length of 0.55 mm. As can be seen from FIG. 34, if the impurity concentration of N.sup.- -drain region is 3.times.10.sup.14 cm.sup.-2 (circular marks in the figure), it is difficult to ensure the above breakdown voltage (6 V). Thus, if the N.sup.- -drain region is formed for reducing the interband tunnel current (leak current), the punch-through phenomenon is likely to occur, resulting in reduction of the drain breakdown voltage.
Further, in the flash memory of the DINOR type, there has been the demand for low cost. In order to meet the demand for low cost, it is necessary to employ common structures for the N-channel transistor in the peripheral circuit and the N-channel transistor in the memory cell region. In general, channel doping for the N-channel transistor in the peripheral circuit is performed by implanting boron with implantation energy of about 50 keV. However, if channel doping were performed on the memory cell transistor with the same implantation energy, the punch-through phenomenon would be likely to occur in the memory cell transistor provided with N.sup.- -drain region 4.
If implantation dose of impurity for the channel doping is increased in order to overcome the above problem, such a problem arises that the threshold voltage of peripheral transistor increases and the drain current decreases. If the implantation energy for channel doping is increased, such a problem arises that a substrate constant K at the peripheral transistor increases. Description will be given more in detail on the facts that the punch-through phenomenon is likely to generate if N.sup.- -drain region 4 is formed, and that the substrate constant K of peripheral transistor increases if the implantation energy increases.
FIG. 35 shows an impurity profile at the channel portion in the memory cell, and FIG. 36 shows an impurity profile at the drain portion in the memory cell. Referring to FIG. 35, a curve portion having a peak at about 0.14 .mu.m from the substrate surface represents impurity distribution caused by the channel doping. A curve portion having a peak at about 0.37 .mu.m represents impurity distribution in the channel stopper layer. It can be understood that the concentration of P-type impurity is low at about 0.22 .mu.m from the substrate. If N.sup.- -drain region 4 is formed for the purpose of reducing the leak current of memory cell transistor, the punch-through phenomenon is likely to occur in a region at a depth of about 0.22 .mu.m from the substrate, because the impurity concentration is low at this region. FIG. 37 shows punch-through characteristics in the case where the gate length of 0.4 .mu.m is set in the memory cell transistor having the impurity profiles shown in FIGS. 35 and 36. It can be seen from FIG. 37 that a depletion layer spreads at a deep region of the substrate from the drain to the source if a potential of about 5 V is applied to the drain.
Now, the reason by which the substrate constant K of peripheral transistor increases if the implantation energy for channel doping increases will be described below. FIG. 38 shows impurity profiles in the case where the channel doping is effected with the implantation energy of 50 keV and the implantation energy of 60 keV. Referring to FIG. 38, a nearly equal threshold voltage is achieved with implantation energies of 50 keV and 60 keV. For achieving the nearly equal threshold voltage, it is necessary to provide a nearly equal impurity concentration at the surface of substrate, and for this purpose, implantation doses of impurity are adjusted depending on the implantation energies of 50 keV and 60 keV. More specifically, if the implantation energy is 60 keV, the impurity ion is implanted more deeply than the case of impurity implantation energy of 50 keV, so that the impurity concentration at the surface of substrate is small. Therefore, if the implantation energy is 60 keV, it is necessary to implant more impurity than that implanted with implantation energy of 50 keV. In this manner, the nearly equal implantation concentration is achieved at the surface of substrate with the implantation energies of 50 keV and 60 keV. At a region B in FIG. 38, the impurity concentration achieved with the implantation energy of 50 keV is higher than that achieved with 60 keV. Therefore, if the implantation energy is 60 keV, the depletion layer is suppressed more effectively from spreading between the source region and drain region, so that the punch-through phenomenon can be suppressed more effectively.
At a region A, the implantation energy of 60 kev achieve a higher impurity concentration than the implantation energy of 50 keV. Even when the substrate bias voltage is applied, the implantation energy of 60 kev achieves a higher impurity concentration at the region A in the substrate than the implantation energy of 50 keV. This means that the implantation energy of 60 keV suppresses the spreading of depletion layer toward the substrate as compared with the implantation energy of 50 keV. Therefore, if the implantation energy is 60 keV, a gate bias voltage must be larger than that in the case of implantation energy of 50 keV in order to obtain the channel current nearly equal to that obtained by the implantation energy of 50 keV. This means that, if the implantation energy is 60 keV, the substrate constant K is larger than that in the case of 50 keV.
As described above, if the conventional flash memory of the DINOR type is provided with N.sup.- -drain region 4 for reducing the interband tunnel current (leak current) in the memory cell transistor, such a problem arises that the punch-through phenomenon is likely to occur in the memory cell transistor. If the implantation dose of impurity for channel doping is increased in order to increase the resistance to punch-through phenomenon, such problems arise that the threshold voltage of transistor in the peripheral circuit increases and that the drain current decreases, and increase of the implantation energy for the channel doping results in a problem that the substrate constant K of the transistor in the peripheral circuit increases.